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Single-chip Type with Built-in FET Switching Regulator Series
Output 1.5A or Less High Efficiency Step-down Switching Regulator with Built-in Power MOSFET
BD9153MUV
No.09027EAT40
Description ROHM's high efficiency dual step-down switching regulators and Linear Regulator Controller, BD9153MUV is a power supply designed to produce a low voltage including 3.3,0.8 volts from 5.5/4.5 volts power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load. Features 1) Offers fast transient response with current mode PWM control system. 2) Offers highly efficiency for all load range with synchronous rectifier (Pch/Nch FET) and SLLMTM (Simple Light Load Mode) 3) Incorporates Nch FET controller for Linear Regulator. 4) Incorporates reset function with 50ms counter. 5) Incorporates soft-start fanction, thermal protection and ULVO functions. 6) Incorporates short-current protection circuit with time delay function. 7) Incorporates shutdown function Icc=0A(Typ.) 8) Employs small surface mount package : VQFN024V4040 Applications Power supply for LSI including DSP, Micro computer and ASIC Absolute Maximum Rating (Ta=25) Parameter Symbol Vcc,PVcc Voltage VCC,PVCC FB1,FB2,FB3,VS Voltage VFB1, VFB2, VFB3, VVS SW1,SW2,ITH1,ITH2 Voltage VSW1, VSW2, VITH1, V ITH2 EN,RST,DET,GATE Voltage V EN, V RST, V DET, V GATE Pd1 Pd2 Power Dissipation Pd3 Pd4 Operating Temperature Range Topr Storage Temperature Range Tstg Maximum Junction Temperature Tjmax
1 2 3 4 5
Limit -0.3+7*1 -0.3+7 -0.3+7 -0.3+7 2 0.34* 0.69 *3 2.20 *4 3.56*5 -40+85 -55+150 +150
Unit V V V V W W W W
Pd should not be exceeded.
IC only
1-layer. mounted on a 74.2mmx74.2mmx1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 4-layer. mounted on a 74.2mmx74.2mmx1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 , in 1,4 layer, 5505mm2 in 2,3 layer 4-layer. mounted on a 74.2mmx74.2mmx1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers
Operating Conditions (Ta=-40+85) Parameter Vcc Voltage EN Voltage Output Voltage range SW Average Output Current
6
Symbol VCC VEN VOUT1 VOUT2 VOUT3 ISW1 ISW2
Min. 4.5 0 1.8 0.8 0.8 -
Typ. 5.0 -
Max. 5.5 5.5 3.3 2.5 2.5 1.5*6 1.5*6
Unit V V V V V A A
Pd should not be exceeded.
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1/18
2009.08 - Rev.A
BD9153MUV
Electrical Characteristics (Ta=25 VCC=5V, EN=VCC ,unless otherwise specified.) Parameter Standby Current Bias Current EN Low Voltage EN High Voltage EN Input Current Oscillation Frequency Pch FET ON Resistance Nch FET ON Resistance FB Reference Voltage ITH sink curren1 ITH source current 1 ITH sink curren2 ITH source current 2 UVLO Threshold Voltage1 UVLO Release Voltage1 UVLO Threshold Voltage2 UVLO Release Voltage2 VS Discharge Resistance Soft Start Time Timer Latch Time Output Short circuit Threshold Voltage RST Release Voltage RST threshold Voltage RST Delay RST ON Reststance GATE Source Current GATE Sink Current Symbol ISTB ICC VENL VENH IEN FOSC RONP1 RONP2 RONN1 RONN2 VFB1,2 VFB3 VFB3 ITHSI1 ITHSO1 ITHSI2 ITHSO2 VUVLOL1 VUVLOH1 VUVLOL2 VUVLOH2 RVS TSS TLATCH VSCP1 VSCP2 VSCP3 VRST1 VRST2 TRST RONRST IGSO IGSI Min. 2 0.8 0.788 0.784 0.780 10 10 10 10 3.6 3.65 2.4 2.425 0.4 1.0 0.691 0.668 40 0.5 1.0 Limit Typ. 0 600 GND Vcc 2 1.0 0.17 0.17 0.13 0.13 0.8 0.8 0.8 18 18 18 18 3.8 3.9 2.5 2.55 40 0.8 2.0 0.4 0.4 0.4 0.720 0.696 50 140 1.5 5.0 Max. 10 1000 0.8 10 1.2 0.3 0.3 0.2 0.2 0.812 0.816 0.820 4.0 4.2 2.6 2.7 80 1.6 4.0 0.56 0.56 0.56 0.749 0.724 60 280 Unit A A V V A MHz V V V A A A A V V V V ms ms V V V V V ms mA mA
Technical Note
Condition EN=0V Standby Mode Active Mode EN=2V Vcc=5V Vcc=5V Vcc=5V Vcc=5V 1.5% 2.0%(Ta=25) 2.5%(Ta=-40~+85) VFB1=1.0V VFB1=0.6V VFB2=1.0V VFB2=0.6V Vcc=50V Vcc=05V Vcc=50V Vcc=05V Vcc=5V SCP/TSD ON FB1=0.80V FB2=0.80V FB3=0.80V DET=0V0.8V DET=0.8V0V
VFB3=0.6V , VGATE=2.5V VFB3=1.0V , VGATE=2.5V
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2/18
2009.08 - Rev.A
BD9153MUV
Block Diagram, Application Circuit
Technical Note
4.00.1
4.00.1
D9153
OUT1 FB1
Gm Amp
PVCC
Current Comp R S Slope1 Q
Current Sense/ Protect + Driver Logic
SW1
OUT1
Lot No.
EN ITH1
Soft Start1
1.0Max.
PGND1
S
SCP1
0.02 +0.03 -0.02 (0.22)
CLK1
0.08 S
VREF
OSC
CLK2
SCP/ TSD
UVLO1 UVLO2
C0.2 2.40.1
1 6
SCP2
PVCC
Current
0.40.1
24
2.40.1
7
OUT2 FB2
Gm Amp
Current Comp R S Slope2 Q
Sense/ Protect + Driver Logic
19 18
12 13
SW2
OUT2
0.75 0.5
0.25 +0.05 -0.04
ITH2
Soft Start2
CLK2
PGND2
(Unit : mm) Fig.1 BD9153MUV TOP View
DET
Soft Start1
OUT1 GATE
SCP3
FB3 OUT3 VS
RST
Timer
ITH1
SCP/TSD UVLO1
FB1
AGND
PGND1
Fig.2 BD9153MUV Block Diagram
Pin No. & function table Pin No. Pin name 1 2 3 4 5 6 7 8 9 10 11 12 PGND2 PVCC2 PVCC2 PVCC1 PVCC1 PGND1 PGND1 SW1 SW1 VS FB1 ITH1
Function
Pin No. 13 14 15 16 17 18 19 20 21 22 23 24
Pin name GATE FB3 AVCC DET RST AGND ITH2 FB2 EN SW2 SW2 PGND2 Gate drive pin
Function Output Voltage3 detector pin AVCC power supply input pin Voltage detector pin RST signal output pin Ground GmAmp2 output pin Output Voltage2 detector pin Enable pin (High Active) SW pin (2ch) SW pin (2ch) Nch FET Source pin (2ch)
Nch FET Source pin (2CH) Pch FET Source pin (2CH) Pch FET Source pin (2CH) Pch FET Source pin (1CH) Pch FET Source pin (1CH) Nch FET Source pin (1CH) Nch FET Source pin (1CH) SW pin (1ch) SW pin (1ch) Discharge function pin Output Voltage1 detector pin GmAmp1output pin
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3/18
2009.08 - Rev.A
BD9153MUV
Characteristics dataBD9153MUV
3.5
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
Technical Note
4.0
3.5
VOUT1=3.3V
OUTPUT VOLTAGE:VOUT[V]
3.0 2.5 2.0 1.5 1.0 0.5 0.0 0
Ta=25 Io=1.5A VOUT1=3.3V VOUT2=1.2V
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
3.0 2.5 2.0 1.5 1.0 0.5 0.0
VOUT1=3.3V
VCC=5V VOUT2=1.2V Ta=25 Io=0A
0 1 2 3 4 EN VOLTAGE:VEN[V] 5
VOUT2=1.2V
VCC=5V Ta=25
1
2 3 4 INPUT VOLTAGE:VCC[V]
5
0
1 2 3 OUTPUT CURRENT:IOUT [A]
4
Fig.3 VCC - VOUT1,VOUT2
3.40
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
Fig.4 VEN - VOUT
1.25
100
Fig.5 IOUT - VOUT
VOUT1=3.3V
3.35
1.23
VOUT2=1.2V VOUT2=1.2V
EFFICIENCY:[%]
90 80 70 60 50 40 30 20 10
3.30
1.20
VOUT1=3.3V
VOUT2=1.2V
3.25
1.18
VCC=5V Io=0A
3.20 -40 -20 0 20 40 60 TEMPERATURE:Ta[] 80
VCC=5V Io=0A
-40 -20 0 20 40 60 TEMPERATURE:Ta[] 80
VCC=5V Ta=25
1.15
0 10 100 1000 OUTPUT CURRENT:IOUT[mA] 10000
Fig. 6 Ta-VOUT1
1.2 1.0 FREQUENCY:FOSC[MHz] 0.8 0.6 0.4 0.2 0.0
-40 -20 0 20 40 60 80
Fig. 7 Ta-VOUT2
Fig.8 Efficiency
250 225 200 175 150 125 100 75 50 25 0
1.2
VCC=5V PMOS
FREQUENCY:FOSC[MHz]
1
ON RESISTANCE:RON[m]
1.1
NMOS
0.9
VCC=5V
Ta=25
0.8 4.5
TEMPERATURE:Ta[]
4.75 5 5.25 INPUT VOLTAGE:VCC[V]
5.5
-40
-20
0 20 40 60 80 TEMPERATURE:Ta[]
100
Fig.9 Ta- Fosc
2.0 1.8 1.6
EN VOLTAGE:VEN[V]
Fig.10 VCC-Fosc
600 CIRCUIT CURRENT:ICC[A] 500
Fig.11 Ta - RONN, RONP
VCC=5V,Ta=25
EN
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
-40 -20 0 20 40 60 80
400 300 200 100 0
-40 -20 0 20 40 60 80
VOUT1
EN1=E2 VOUT1
VCC=5V
VOUT2
VCC=5V
VOUT3
TEMPERATURE:Ta[]
VOUT2
VCC=5.0V Ta=25
TEMPERATURE:Ta[]
Fig.12 TaEN
Fig.13 TaIcc
Fig.14 Soft start wave form (Io1=0mA, Io2=0mA, Io3=0mA)
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4/18
2009.08 - Rev.A
BD9153MUV
Technical Note
EN SW1 VOUT1 SW1
VOUT2
VOUT1
VOUT1
VOUT3
VCC=5.0V Ta=25
VCC=5.0V,Vout1=3.3V Ta=25
VCC=5.0V,Vout1=3.3V Ta=25
Fig.15 Soft start wave form (Io1=1.5A, Io2=1.5A, Io3=1.0A)
Fig.16 SW1 wave form (Io1=0mA)
Fig.17 SW1 wave form (Io1=1.5A)
SW2
SW2
VOUT1
VOUT2
VOUT2
IOUT1
VCC=5.0V,Vout2=1.2V Ta=25
VCC=5.0V,Vout2=1.2V Ta=25
VCC=5.0V,Vout1=3.3V Ta=25
Fig.18 SW2 wave form (Io2=0mA)
Fig.19 SW2 wave form (Io2=1.5A)
Fig.20 VOUT1 transient responce (Io10.5A1.5A / 10usec)
VOUT1
VOUT2
VOUT2
IOUT1
IOUT2
IOUT2
VCC=5.0V,Vout1=3.3V Ta=25
VCC=5.0V,Vout2=1.2V Ta=25
VCC=5.0V,Vout2=1.2V Ta=25
Fig.21 VOUT1 transient responce (Io11.5A0.5A/ 10usec)
Fig.22 VOUT2 transient responce (Io20.5A1.5A/ 10usec)
Fig.23 VOUT2 transient responce (Io21.5A0.5A/ 10usec)
VOUT3
VOUT3
IOUT3
IOUT3
VCC=5.0V,Vout3=2.5V Ta=25
VCC=5.0V,Vout3=2.5V Ta=25
Fig.24 VOUT3 transient responce (Io30.5A1A/ 10usec)
Fig.25 VOUT3 transient responce (Io3500mA1A/ 10usec)
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5/18
2009.08 - Rev.A
BD9153MUV
Information on advantages Advantage 1Offers fast transient response with current mode control system. BD9153MUV (Load response IO=0.5A1.5A / usec)
Technical Note
BD9153MUV (Load response IO=1.5A0.5A / usec)
VOUT1
VOUT1
Io1
Io1
Fig.26 Advantage 2 Offers high efficiency for all load range. For lighter load: Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load. For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. ON resistance of Highside MOS FET : 170m(Typ.) ON resistance of Lowside MOS FET : 130m(Typ.)
100 Efficiency [%] SLLMTM 50 PWM
inprovement by SLLM system improvement by synchronous rectifier
Achieves efficiency improvement for heavier load. Offers high efficiency for all load range with the improvements mentioned above.
0 0.001
0.01 0.1 Output current Io[A]
1
Fig.27 Efficiency
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6/18
2009.08 - Rev.A
BD9153MUV
Technical Note
Advantage 3Supplied in smaller package due to small-sized power MOS FET incorporated. Output capacitor Co required for current mode control: 22F ceramic capacitor Inductance L required for the operating frequency of 1 MHz: 2.2H inductor Incorporates FET + Boot strap diode Reduces a mounting area required.
R5 Cfb
R6
50mm
CO3 M1
COUT1 CIN1 CIN2
COUT2
R9 CITH2 RITH2 RITH1 CITH1
AGND ITH2 FB2 EN
RST
DET
AVCC
FB3 GATE ITH1 FB1 VS SW 1
50mm
R2 R1 RITH1
RITH2 R3 R8 R9
R4
L2 CO2
SW2
L1
M1
SW2 PGND2 SW1 PGND1 CO1 R2
CITH1
R4
R3
PGND2 PVCC2 PVCC2 PVCC1 PVCC1 PGND1
R1
R5 C1 R6 COUT3 R7
CIN2
CIN1
R8
R7
Fig.28
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7/18
2009.08 - Rev.A
BD9153MUV
Technical Note
Operation BD9153MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency. Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a highside MOS FET (while a lowside MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET (while a lowside MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation.
TM SLLM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency.
SENSE Current Comp RESET Level Shift Gm Amp. ITH OSC RQ FB SET S Driver Logic SW Load IL VOUT
VOUT
Fig.29 Diagram of current mode PWM control
SENSE PVCC Current Comp SET RESET SW IL GND IL(AVE) IL FB GND GND RESET SW Current Comp SET
PVCC SENSE FB GND GND
GND 0A
VOUT
VOUT(AVE)
VOUT
VOUT(AVE)
Not switching
Fig.30 PWM switching timing chart
Fig.31 SLLM
TM
switching timing chart
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8/18
2009.08 - Rev.A
BD9153MUV
Technical Note
Description of operations Soft-start function EN terminal shifted to "High" activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. Shutdown function With EN terminal shifted to "Low", the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0A (Typ.).
RST function If DET voltage over 0.72V(Typ.), RST terminal shifted to "High" after 50ms(Typ.) delay. And the hysteresis width of 24mV (Typ.) is provided to prevent output chattering. UVLO function Detects whether the input voltage sufficient to secure the output voltage of BU9153MUV is supplied. And the hysteresis width of 100mV (UVLO1 Typ.) ,50mV(UVLO2 Typ.) is provided to prevent output chattering. Each the outputs have UVLO. It is possible to set output sequence easy.
4.5V detect (RST Release voltage x6.25) 3.9V detect (UVLO Release voltage 1) 2.55V detect (UVLO Release voltage2)
4.35V (RST Threshold Voltage x6.25) 3.8V (UVLO Threshold Voltage 1) 2.5V (UVLO Threshold Voltage 2)
VCCEN 3.3V Output (DC/DC 1) 2.5V Output (LDO) 1.2V Output (DC/DC 2)
VS discharge ON
Output
0.8ms Soft-start 50ms (RST Delay)
RST
Natural discharge
RST
Fig.32 Soft-start, Shutdown, RST Delay, UVLO, timing chart
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9/18
2009.08 - Rev.A
BD9153MUV
Technical Note
Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO.
EN Output Short circuit Threshold Voltage OUT1 Output OFF Latch OUT2 OUT3
IL Limit
Io1
Io2
Io3
t1t2t3=TLATCH Standby mode Operating mode
EN
Timer latch
EN
Fig.33 Short-current protection circuit with time delay timing chart Switching regulator efficiency Efficiency may be expressed by the equation shown below: = VOUTxIOUT VinxIin x100[%]= POUT Pin x100[%]= POUT POUT+PD x100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PD as follows: Dissipation factors: 2 1) ON resistance dissipation of inductor and FETPD(I R) 2) Gate charge/discharge dissipationPD(Gate) 3) Switching dissipationPD(SW) 4) ESR dissipation of capacitorPD(ESR) 5) Operating current dissipation of ICPD(IC) 1)PD(I R)=IOUT x(RCOIL+RON) (RCOIL[]DC resistance of inductor, RON[]ON resistance of FET, IOUT[A]Output current.) 2)PD(Gate)=CgsxfxV (Cgs[F]Gate capacitance of FET, f[H]Switching frequency, V[V]Gate driving voltage of FET) 3)PD(SW)= Vin2xCRSSxIOUTxf IDRIVE (CRSS[F]Reverse transfer capacitance of FET, IDRIVE[A]Peak current of gate.)
2 2
2 4)PD(ESR)=IRMS xESR (IRMS[A]Ripple current of capacitor, ESR[]Equivalent series resistance.) 5)PD(IC)=VinxICC (ICC[A]Circuit current.)
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10/18
2009.08 - Rev.A
BD9153MUV
Technical Note
Consideration on permissible dissipation and heat generation As BU9153MUV functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation.
4.0
3.56W
4 layers (copper foil area : 5505mm ) (Copper foil in each layers) j-a=35.1/W 2 4 layers (copper foil area : 10.29mm ) (Copper foil in 2nd and 3rd layers) j-a=56.8/W 2 1 layer (Copper foil area : 0mm ) j-a=181.2/W IC only j-a=367.6/W
2
P=IOUT2xRON RON=DxRONP+(1-D)RONN DON duty (=VOUT/VCC) RONHON resistance of Highside MOS FET RONLON resistance of Lowside MOS FET IOUTOutput current
3.0 Power dissipation : Pd [W]
2.2W
2.0
1.0
0.69W 0.34W
0 0
25
SW1 75 100 105 125 Ambient temperature :Ta []
150
Fig.34 Thermal derating curve (VQFN024V4040) (Example) VCC=5V, VOUT1=3.3V, VOUT2=1.2V, RONH=170m, RONL=130m IOUT=1.5A, for example, D1=VOUT1/VCC=3.3/5=0.66 D2=VOUT2/VCC=1.2/5=0.24 RON1=0.66x0.170+(1-0.66)x0.130 =0.1122+0.0442 =0.1564[] RON2=0.24x0.170+(1-0.24)x0.130 =0.0408+0.0988 =0.1397[]
2 2 P=1.5 x0.1564+1.5 x0.1397=0.666[W]
As RONH is greater than RONL in BU9153MUV, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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11/18
2009.08 - Rev.A
BD9153MUV
Selection of components externally connected 1. Selection of inductor (L)
IL IL
Technical Note
The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. (VCC-VOUT)xVOUT LxVCCxf
VCC
IL=
[A](1)
IL VOUT L Co
Appropriate ripple current at output should be 20% more or less of the maximum output current. IL=0.2xIOUTmax. [A](2) L= (VCC-VOUT)xVOUT ILxVCCxf [H](3)
Fig.35 Output ripple current
(IL: Output ripple current, and f: Switching frequency)
Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=5.0V, VOUT=1.2V, f=1.0MHz, IL=0.3x1.5A=0.45A, for example,(BD9153MUV) (5-1.2)x1.2 0.45x5x1.0M
L=
=2.02 2.2[H]
Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency.
2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage.
VOUT
Output ripple voltage is determined by the equation (4) VOUT=ILxESR [V](4) (IL: Output ripple current, ESR: Equivalent series resistance of output capacitor) Rating of the capacitor should be determined allowing sufficient margin against output voltage. A 22F to 100F ceramic capacitor is recommended. Less ESR allows reduction in output ripple voltage.
L
ESR Co
Fig.36 Output capacitor
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12/18
2009.08 - Rev.A
BD9153MUV
3. Selection of input capacitor (Cin)
VCC
Technical Note
Cin
Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. ripple current IRMS is given by the equation (5):
VOUT
The
L
Co
IRMS=IOUTx
VOUT(VCC-VOUT)
VCC < Worst case > IRMS(max.)
[A](5)
Fig.37 Input capacitor
2 If VCC=5.0V, VOUT=1.8V, and IOUTmax.=1.5A, (BD9153MUV) IRMS=2x 1.8(5.0-1.8) 5.0 = 0.48[ARMS]
When Vcc=2xVOUT, IRMS =
IOUT
A low ESR 22F/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency. 4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.) A Gain [dB] fp(Max.) 0 fz(ESR) IOUTMin. 0 IOUTMax.
fp=
1 2xROxCO
fz(ESR)=
Phase [deg]
1 2xESRxCO Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. fp(Min.)= 1 [Hz]with lighter load 2xROMax.xCO 1 2xROMin.xCO [Hz] with heavier load
-90
Fig.38 Open loop gain characteristics fp(Max.)=
A Gain [dB] 0 0 Phase [deg] -90
fz(Amp.)
Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.) fz(Amp.)= 1 2xRITHxCITH
Fig.39 Error amp phase compensation characteristics
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13/18
2009.08 - Rev.A
BD9153MUV
Technical Note
R5 Cfb
R6 CO3
R9
M1 DET AVCC FB3 GATE ITH1 FB1 RITH1 CITH1
CITH2
RITH2
AGND ITH2 FB2
RST
EN
VS SW1
L2
SW2
L1
R4
CO2
SW2 PGND2
SW1 PGND1 PVCC2 PVCC2 PVCC1 PVCC1 PGND1
CO1
R2
R3
PGND2
R1
CIN2
CIN1
R8
R7
Fig.40 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 2xRITHxCITH = 1 2xROMax.xCO
5. Determination of VOUT1~3 output voltage The output voltage VOUT1~3 is determined by the equation (6)~(8): VOUT1=(R2/R1+1)xVFB1(6) VFB1: Voltage at FB terminal (0.8V Typ.) VOUT2=(R4/R3+1)xVFB2(7) VFB2: Voltage at FB terminal (0.8V Typ.) VOUT3=(R6/R5+1)xVFB3(8) VFB3: Voltage at FB terminal (0.8V Typ.) With R1~R6 adjusted, the output voltage may be determined as required.
L1 VOUT1 SW1 Cout1 R2
FB1
R1
Fig.41 Determination of output voltage Use 1 k100 k resistor for R1. If a resistor of the resistance higher than 100 k is used, check the assembled set carefully for ripple voltage etc.
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14/18
2009.08 - Rev.A
BD9153MUV
BD9153MUV Cautions on PC Board layout Silk screen Top Layer
Technical Note
Bottom Layer
Fig.42 Layout diagram

Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. VQFN024V4040 (BD9153MUV) has thermal PAD on the reverse of the package. The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of PCB.
Recommended components Lists on above application Symbol L1,2 CIN1,CIN2 Cout1,Cout2 CITH1 RITH1 CITH2 RITH2 Cfb M1 Coil Ceramic capacitor Ceramic capacitor Ceramic capacitor Resistance Ceramic capacitor Resistance Ceramic capacitor Nch MOS FET Part Value 2.2H 22F 22F VOUT1=3.3V VOUT1=3.3V VOUT2=1.2V VOUT2=1.2V 56pF 680pF 39k 680pF 12k Manufacturer TDK Murata Murata Murata Rohm Murata Rohm Murata Rohm Series LTF5022-2R2N3R2 GRM32EB11A226KE20 GRM31CB30J226KE18 GRM18 Series MCR03 Series GRM18 Series MCR03 Series GRM18 Series RTF015N03
The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and BU9153MUV when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins.
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15/18
2009.08 - Rev.A
BD9153MUV
I/O equivalence circuit
EN pin SW1,SW2 pin
PVCC PVCC PVCC
Technical Note
EN SW1,SW2
FB1,FB2,FB3,DET pin
FB1,FB2,FB3,DET
ITH1,ITH2 pin
AVCC
ITH1,ITH2
RST, VS pin
RST,VS
GATE pin
AVCC
GATE
Fig.43 I/O equivalence circuit
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16/18
2009.08 - Rev.A
BD9153MUV
Technical Note
Notes for use 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 5. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 6. Input to IC terminals + This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 44. P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements.
Resistor Pin A Pin A
P
+
Transistor (NPN)
EN C B E B P P
+
Pin B
N P P
+
N N
P+
N N
C E
N
P substrate
GND
Parasitic element
P substrate
GND GND GND
Parasitic element
Parasitic element
Parasitic element
Other adjacent elements
Fig.44 Simplified structure of monorisic IC 7. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 8 . Selection of inductor It is recommended to use an inductor with a series resistance element (DCR) 0.15 or less. Note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF. When using an inductor over 0.15, be careful to ensure adequate margins for variation between external devices and BU9153MUV, including transient as well as static characteristics.
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17/18
2009.08 - Rev.A
BD9153MUV
Ordering part number
Technical Note
B
D
9
Part No.
1
5
3
M
U
V
-
E
2
Part No.
Package MUV: VQFN24V4040
Packaging and forming specification E2: Embossed tape and reel (VQFN24V4040)
VQFN024V4040
4.00.1
4.00.1

Tape Quantity Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
1.0MAX
1PIN MARK S
+0.03 0.02 -0.02 (0.22)
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
0.08 S C0.2
1 24
2.40.1
6
0.40.1
19 18 13
12
0.75
0.5
2.40.1
7
+0.05 0.25 -0.04
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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18/18
2009.08 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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